Present direct conversion receiver (DCR) architectures often incorporate a dynamically matched architecture that uses a single reference signal source which operates at two times the carrier frequency. This generates both the local oscillator (LO) signal and a mitigation frequency reference signal which is typically less than 300 MHz. To avoid “self quieting” interference between the LO and the mitigation signals as well as their harmonics, the mitigation frequency reference signal is generated by using odd integer dividers to generate odd integer sub-multiples of the voltage controlled oscillator (VCO) frequency. The LO frequency is generated by dividing down the VCO frequency by an even multiple for an even integer divider or by an odd multiple for an odd multiple divider. While this arrangement is typically used in DCR architectures, further optimization is necessary to provide margin to system receiver requirements such as terrestrial trunked radio (TETRA) blocking and frequency modulated digital private line (FM DPL) distortion mitigation. In-phase (I) and quadrature (Q) matching directly influences sideband suppression which, in turn, directly affects the generation of sub-audible signaling distortion products. In addition, excessive I and Q mismatch can degrade second order intercept point (IP2) performance which bears directly on the receiver's interference blocking performance.
Prior art dynamically matched mixer systems include U.S. Pat. No. 6,125,272 to Bautista et al. that teaches a method and apparatus for providing improved intermodulation distortion protection. U.S. Pat. No. 6,125,272 is herein incorporated by reference. The prior art techniques involve the use of dynamic matching to transform coefficients of the IM2 distortion from constant values into functions of time where they may be handled by known rejection techniques. This involves using odd and even integer dividers used to divide down from a single VCO source so that an even division multiple is used with the LO and the odd division multiple is used for quadrature generation. Thus, there is a finite point at which the divider multiple will create an even multiple mixed with the odd multiple causing a “spur” which self quiets the receiver. This relationship between even and odd frequency relationship can be a problem in this type of design. The system as defined by Bautista et al. limits the overall benefit of this dynamically matched mixer design since it decreases the receiver's IP2 performance by randomizing the second order distortion product. Thus, Bautista et al. fail to address system level implementation issues that can degrade I/Q channel matching due to mitigation coupling between the LO quadrature generation circuitry and reference signal mitigation circuitry.
The prior art dynamically matched differential I channel mixer 100 is illustrated in prior art FIG. 1, where reference oscillator 101 and PLL 103 represent a phase locked loop that provides a stable radio frequency (RF) source at some predetermined frequency. The PLL 103 provides differential inputs to a plurality of frequency harmonic dividers namely Neven divider 105 and Nodd divider 107. Each respective harmonic divider provides a means to provide an even or odd multiple harmonic frequency from the source provided by PLL 103. The output of the Neven divider 105 provides local oscillator (LO) differential inputs (FLO+ and FLO−) to a mixer 109 while the output of the Nodd divider 107 supplies a mitigation signal (F1) to both the dynamic matching network 111 and the dynamic matching network 113.
As will be recognized by those skilled in the art, the mixer 109 is a standard Gilbert cell mixer which enables differential RF input signals (IRF+ and IRF−) to be mixed with both the LO differential signal (FLO+ and FLO−) and mitigation signal F1. The dynamic matching network 111 and dynamic matching network 113 are essentially a switching network. These switching networks switch between transistor components within the in-phase (I) or quadrature (Q) mixer branches so as to average imperfections in the mixer's components to provide substantially enhanced mixer linearity. A plurality of alternating current (AC) couplers 115, 116 are used to couple the mixer 109 and dynamic matching network 113 which helps to eliminate temperature compensating direct current (DC) mismatch, improves system common mode rejection of the dynamic mixer and eliminates the use of an 1/f noise adder by the LO. Finally, the differential baseband output signals (IBB+ and IBB−) for either an in-phase or quadrature channel is provided at an output of the dynamic matching network 113. As noted with other prior art designs, the circuit topology of prior art FIG. 1 creates a spur which causes problems depending on what harmonics are used at the LO and the mitigation signal F1. As will be recognized by those skilled in the art, prior art FIG. 1 shows a differential I-channel mixer while a differential Q-channel mixer will be similarly configured.
Therefore, it would be advantageous to provide a system and method of using a dynamic matched mixer which provides improved second order intermodulation distortion (IP2) performance. It would also be advantageous to apply this system and method to wireless and wireline communications devices that employ mixer circuits, switches, and other components that exhibit parametric mismatch or imbalance.